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note : all information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publi cation; however, this data sheet cannot be a ?controlled document?. current revisions, if any, to these specifications are maintained at the factory and are available upon your request. we recommend checking the revision level befor e finalization of your design documentation. ? 2001 elantec semiconductor, inc. e l 7 5 6 4 c general description the el7564c is an integrated, full-featured synchronous step-down regulator with output voltage adjustable from 1.0v to 3.8v. it is capa- ble of delivering 4a continuous current at up to 95% efficiency. the el7564c operates at a constant frequency pulse width modulation (pwm) mode, making external synchronization possible. patented on- chip resistorless current sensing enables current mode control, which provides cycle-by-cycle current limiting, over-current protection, and excellent step load response. the el7564c features power tracking, which makes the start-up sequencing of multiple converters possible. a junction temperature indicator conveniently monitors the silicon die temperature, saving the designer time on the tedious thermal charac- terization. the minimal external components and full functionality make this el7564c ideal for desktop and portable applications. the el7564c is specified for operation over the -40c to +85c tem- perature range. typical application diagrams manufactured under u.s. patent no. 5,7323,974 1 2 3 4 16 15 14 13 5 6 7 12 11 9 8 10 el7564cm (20-pin so) 20 19 18 17 0.1f 390pf 0.22f 22 w 2.2nf 330f v in 5v v out 3.3v, 4a 2.37k 1k w 330f 0.22f 4.7h vref sgnd cosc vdd vtj pgnd pgnd vin stp stn en fb pg vdrv vhi lx lx pgnd pgnd pgnd 2.2nf c5 c4 r4 c3 c2 c1 c6 d1 l1 c7 r2 c10 r1 typical application diagrams continued on page 3 features ? integrated synchronous mosfets and current mode controller ? 4a continuous output current ? up to 95% efficiency ? 4.5v to 5.5v input voltage ? adjustable output from 1v to 3.8v ? cycle-by-cycle current limit ? precision reference ? 0.5% load and line regulation ? adjustable switching frequency to 1mhz ? oscillator synchronization possible ? internal soft start ? over voltage protection ? junction temperature indicator ? over temperature protection ? under voltage lockout ? multiple supply start-up tracking ? power good indicator ? 20-pin so (0.300?) package ? 28-pin htssop package applications ? dsp, cpu core and io supplies ? logic/bus supplies ? portable equipment ? dc:dc converter modules ? gtl + bus power supply ordering information part no package tape & reel outline # el7564cm 20-pin so - mdp0027 el7564cm-t13 20-pin so 13? mdp0027 el7564cre 28-pin htssop - mdp0048 EL7564CRE-T7 28-pin htssop 7? mdp0048 el7464cre-t13 28-pin htssop 13? mdp0048 el7564c monolithic 4 amp dc:dc step-down regulator o c t o b e r 3 , 2 0 0 1
2 el7564c monolithic 4 amp dc:dc step-down regulator e l 7 5 6 4 c absolute maximum ratings (t a = 25c) supply voltage between v in or v dd and gnd +6v v lx voltage v in +0.3v input voltage gnd -0.3v, v dd +0.3v v hi voltage gnd -0.3v, v lx +6v storage temperature -65c to +150c operating ambient temperature -40c to +85c operating junction temperature +135c important note: all parameters having min/max specifications are guaranteed. typ values are for information purposes only. unless otherwise note d, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a . dc characteristics v dd = v in = 5v, t a = t j = 25 c, c osc = 1.2nf, unless otherwise specified. parameter description conditions min typ max unit v ref reference accuracy 1.24 1.26 1.28 v v reftc reference temperature coefficient 50 ppm/c v refload reference load regulation 0 3 el7564c monolithic 4 amp dc:dc step-down regulator e l 7 5 6 4 c typical application diagrams (continued) closed loop ac electrical characteristics v s = v in = 5v, t a = t j = 25c, c osc = 1.2nf, unless otherwise specified. parameter description conditions min typ max unit f osc oscillator initial accuracy 105 117 130 khz t sync minimum oscillator sync width 25 ns m ss soft start slope 0.5 v/ms t brm fet break before make delay 15 ns t leb high side fet minimum on time 150 ns d max maximum duty cycle 95 % el7564cre (28-pin htssop) 1 2 3 4 16 15 14 13 5 6 7 12 11 9 8 10 20 19 18 17 24 23 22 21 28 27 26 25 0.22f 22 w 2.2nf v in 5v v out 3.3v, 4a 2.37k w 1k w 330f 0.22f 4.7h vref sgnd cosc vdd vtj pgnd pgnd pgnd pgnd vin en fb pg vdrv vhi lx lx lx lx lx 2.2nf r4 c3 c2 c6 d1 l1 c7 r2 c10 r1 vin nc stp stn lx nc pgnd pgnd 0.1f 390pf c5 c4 330f for the package information, please refer to the elantec website at http://www.elantec.com/pages/package_outline.html
4 el7564c monolithic 4 amp dc:dc step-down regulator e l 7 5 6 4 c pin descriptions pin number pin name pin function 1 vref bandgap reference bypass capacitor; typically 0.1f to sgnd 2 sgnd control circuit negative supply or signal ground 3 cosc oscillator timing capacitor (see performance curves) 4 vdd control circuit positive supply; normally connected to vin through an rc filter 5 vtj junction temperature monitor; connected with 2.2nf to 3.3nf to sgnd 6 pgnd ground return of the regulator; connected to the source of the low-side synchronous nmos power fet 7 pgnd ground return of the regulator; connected to the source of the low-side synchronous nmos power fet 8 vin power supply input of the regulator; connected to the drain of the high-side nmos power fet 9 stp auxilliary supply tracking positive input; tied to regulator output to synchronize start up with a second supply; leave open for stand alone operation; 2a internal pull down current 10 stn auxilliary supply tracking negative input; connect to output of a second supply to synchronize start up; leave open for stand alone operation; 2a internal pull up current 11 pgnd ground return of the regulator; connected to the source of the low-side synchronous nmos power fet 12 pgnd ground return of the regulator; connected to the source of the low-side synchronous nmos power fet 13 pgnd ground return of the regulator; connected to the source of the low-side synchronous nmos power fet 14 lx inductor drive pin; high current output whose average voltage equals the regulator output voltage 15 lx inductor drive pin; high current output whose average voltage equals the regulator output voltage 16 vhi positive supply of high-side driver; boot strapped from vdrv to lx with an external 0.22f capacitor 17 vdrv positive supply of low-side driver and input voltage for high side boot strap 18 pg power good window comparator output; logic 1 when regulator output is within 10% of target output voltage 19 fb voltage feedback input; connected to external resistor divider between vout and sgnd; a 125na pull-up current forces vout to sgnd in the event that fb is floating 20 en chip enable, active high; a 2a internal pull up current enables the device if the pin is left open; a capacitor can be added at this pin to delay the start of converter
5 el7564c monolithic 4 amp dc:dc step-down regulator e l 7 5 6 4 c typical performance curves (20-pin so package) *power loss vs i o (v in =5v) 2 0 p o w e r l o s s ( w a t t s ) 0.4 0.8 1.2 1.6 0 4 3.5 3 2.5 2 1 0.5 1.5 output current i o (a) v o =3.3v v o =2.8v v o =1.8v 0.5 4 3.5 3 2.5 1.5 1 2 load current i o (a) load regulations (v o =3.3v) 3.275 o u t p u t v o l t a g e ( v ) 3.285 3.295 3.305 3.315 3.325 v in =5v v in =5.5v v in =4.5v line regulation (v o =3.3v) 3.275 v o ( v ) 3.285 3.295 4.5 5.5 5 4.75 5.25 v in (v) 3.325 3.305 3.315 i o =0.5a i o =2a i o =4a v ref vs die temperature 1.27 1.256 1.268 1.266 1.264 1.262 1.26 1.258 -50 150 -10 30 70 110 die temperature (c) v r e f ( v ) *efficiency vs i o (v in =5v) 100 60 65 70 75 85 95 0 4 3.5 3 2.5 2 1 0.5 1.5 load current i o (a) e f f i c i e n c y ( % ) v o =3.3v v o =1.8v 0 4 3.5 3 2.5 2 1 0.5 1.5 load current i o (a) 100 60 65 70 75 95 e f f i c i e n c y ( % ) *efficiency vs i o (v o =3.3v) 90 80 85 v in =4.5v v in =5v v in =5.5v 80 90 v o =2.8v *note: the 28-pin htssop package offers improved performance
6 el7564c monolithic 4 amp dc:dc step-down regulator e l 7 5 6 4 c typical performance curves oscillator frequency vs temperature 360 280 350 340 330 320 310 290 -40 80 -20 20 40 60 temperature (c) o s c i l l a t o r f r e q u e n c y ( k h z ) 0 300 i o =0a i o =4a switching frequency vs c osc 1000 100 900 800 700 500 300 200 100 1000 200 400 600 800 c osc (pf) f s ( k h z ) 900 300 500 700 600 400 vtj vs junction temperature 1.5 0.9 1.3 1.1 0 150 25 junction temperature (c) v t j 125 50 75 100 * q ja vs copper area (20-pin so package) 50 30 46 42 38 34 1 4 1.5 2.5 3.5 pcb copper heat-sinking area (in 2 ) t h e r m a l r e s i s t a n c e ( c / w ) 2 3 with no airflow with 100 lfpm airflow switching waveforms v in =5v, v o =3.3v, i o =4a d v in v lx i l d v o chip in the center of copper area test condition: 1 oz. copper pcb used current limit vs t j 8 3 7 6 5 4 -40 120 -20 40 100 t j (c) i l m t ( a ) 0 80 60 20 v in =4.5v v in =5.5v v in =5v *note: the 28-pin htssop package offers improved performance
7 el7564c monolithic 4 amp dc:dc step-down regulator e l 7 5 6 4 c typical performance curves power-up v in =5v, v o =3.3v, i o =2a power-down v in =5v, v o =3.3v, i o =4a releasing en v in =5v, v o =3.3v, i o =2a shut-down v in =5v, v o =3.3v, i o =4a short-circuit protection v in =5v v in v o v in v o en v o en v o i o v o transient response v in =5v, v o =3.3v, i o =0.2a-4a i o d v o
8 el7564c monolithic 4 amp dc:dc step-down regulator e l 7 5 6 4 c block diagram drivers pwm controller power tracking current sense junction temperature voltage reference oscillator 2.2nf 0.22f 22 w stp stn controller supply sgnd power power fet fet 390pf 0.1f 0.22f 4.7h v out 2370 w 1k w 330f vref cosc vhi vin pgnd vdd vtj vdrv fb d 1 en - + pg vref 2.2nf
9 el7564c monolithic 4 amp dc:dc step-down regulator e l 7 5 6 4 c applications information circuit description general the el7564c is a fixed frequency, current mode con- trolled dc:dc converter with integrated n-channel power mosfets and a high precision reference. the device incorporates all the active circuitry required to implement a cost effective, user-programmable 4a syn- chronous step-down regulator suitable for use in dsp core power supplies. by combining fused-lead packag- ing technology with an efficient synchronous switching architecture, high power output (13w) can be realized without the use of discrete external heat sinks. theory of operation the el7564c is composed of 7 major blocks: 1. pwm controller 2. nmos power fets and drive circuitry 3. bandgap reference 4. oscillator 5. temperature sensor 6. power good and power on reset 7. auxiliary supply tracking pwm controller the el7564c regulates output voltage through the use of current-mode controlled pulse width modulation. the three main elements in a pwm controller are the feed- back loop and reference, a pulse width modulator whose duty cycle is controlled by the feedback error signal, and a filter which averages the logic level modulator output. in a step-down (buck) converter, the feedback loop forces the time-averaged output of the modulator to equal the desired output voltage. unlike pure voltage- mode control systems, current-mode control utilizes dual feedback loops to provide both output voltage and inductor current information to the controller. the volt- age loop minimizes dc and transient errors in the output voltage by adjusting the pwm duty-cycle in response to changes in line or load conditions. since the output volt- age is equal to the time-averaged of the modulator output, the relatively large lc time constant found in power supply applications generally results in low band- width and poor transient response. by directly monitoring changes in inductor current via a series sense resistor the controller's response time is not entirely lim- ited by the output lc filter and can react more quickly to changes in line and load conditions. this feed-forward characteristic also simplifies ac loop compensation since it adds a zero to the overall loop response. through proper selection of the current-feedback to voltage-feed- back ratio the overall loop response will approach a one- pole system. the resulting system offers several advan- tages over traditional voltage control systems, including simpler loop compensation, pulse by pulse current limit- ing, rapid response to line variation and good load step response. the heart of the controller is an input direct summing comparator which sum voltage feedback, current feed- back, slope compensation ramp and power tracking signals together. slope compensation is required to pre- vent system instability that occurs in current-mode topologies operating at duty-cycles greater than 50% and is also used to define the open-loop gain of the over- all system. the slope compensation is fixed internally and optimized for 500ma inductor ripple current. the power tracking will not contribute any input to the com- parator steady-state operation. current feedback is measured by the patented sensing scheme that senses the inductor current flowing through the high-side switch whenever it is conducting. at the beginning of each oscillator period the high-side nmos switch is turned on. the comparator inputs are gated off for a minimum period of time of about 150ns (leb) after the high-side switch is turned on to allow the system to settle. the leading edge blanking (leb) period prevents the detection of erroneous voltages at the comparator inputs due to switching noise. if the inductor current exceeds the maximum current limit (ilmax) a secondary over- current comparator will terminate the high-side switch on time. if ilmax has not been reached, the feedback voltage fb derived from the regulator output voltage vout is then compared to the internal feedback refer- ence voltage. the resultant error voltage is summed with the current feedback and slope compensation ramp. the
10 el7564c monolithic 4 amp dc:dc step-down regulator e l 7 5 6 4 c high-side switch remains on until all four comparator inputs have summed to zero, at which time the high-side switch is turned off and the low-side switch is turned on. however, the maximum on-duty ratio of the high-side switch is limited to 95%. in order to eliminate cross-con- duction of the high-side and low-side switches a 15ns break-before-make delay is incorporated in the switch drive circuitry. the output enable (en) input allows the regulator output to be disabled by an external logic con- trol signal. output voltage setting in general: however, due to the relatively low open loop gain of the system, gain errors will occur as the output voltage and loop-gain is changed. this is shown in the performance curves. a 100na pull-up current from fb to vdd forces vout to gnd in the event that fb is floating. nmos power fets and drive circuitry the el7564c integrates low on-resistance (30m w ) nmos fets to achieve high efficiency at 4a. in order to use an nmos switch for the high-side drive it is nec- essary to drive the gate voltage above the source voltage (lx). this is accomplished by bootstrapping the vhi pin above the lx voltage with an external capacitor cvhi and internal switch and diode. when the low-side switch is turned on and the lx voltage is close to gnd potential, capacitor cvhi is charged through internal switch to vdrv, typically 5v. at the beginning of the next cycle the high-side switch turns on and the lx pins begin to rise from gnd to vin potential. as the lx pin rises the positive plate of capacitor cvhi follows and eventually reaches a value of vdrv+vin, typically 10v, for vdrv=vin=5v. this voltage is then level shifted and used to drive the gate of the high-side fet, via the vhi pin. a value of 0.22f for cvhi is recommended. reference a 1.5% temperature compensated bandgap reference is integrated in the el7564c. the external vref capaci- tor acts as the dominant pole of the amplifier and can be increased in size to maximize transient noise rejection. a value of 0.1f is recommended. oscillator the system clock is generated by an internal relaxation oscillator with a maximum duty-cycle of approximately 95%. operating frequency can be adjusted through the cosc pin or can be driven by an external source. if the oscillator is driven by an external source care must be taken in selecting the ramp amplitude. since cslope value is derived from the cosc ramp, changes to cosc ramp will change the cslope compensation ramp which determine the open-loop gain of the system. when external synchronization is required, always choose c osc such that the free-running frequency is at least 20% lower than that of sync source to accommo- date component and temperature variations. figure 1 shows a typical connection. junction temperature sensor an internal temperature sensor continuously monitors die temperature. in the event that die temperature exceeds the thermal trip-point, the system is in fault state and will be shut down. the upper and low trip-points are set to 135c and 115c respectively. the vtj pin is an accurate indication of the internal sili- con junction temperature (see performance curve.) the v out 0.975 v 1 r 2 r 1 ------ + ? ? ?? = 2 3 16 15 14 13 5 6 7 12 11 9 8 10 19 18 el7564c 1 20 external oscillator bat54s 100pf 390pf figure 1. oscillator synchronization
11 el7564c monolithic 4 amp dc:dc step-down regulator e l 7 5 6 4 c junction temperature t j (c) can be deducted from the following relation: where vtj is the voltage at vtj pin in volts. power good and power on reset during power up the output regulator will be disabled until vin reaches a value of approximately 4v. about 500mv hysteresis is present to eliminate noise-induced oscillations. under-voltage and over-voltage conditions on the regu- lator output are detected through an internal window comparator. a logic high on the pg output indicates that the regulated output voltage is within about +10% of the nominal selected output voltage. power tracking the power tracking pins stp and stn are the inputs to a comparator, whose hi output forces the pwm control- ler to skip switching cycle. 1. linear tracking in this application, it is always the case that the lower voltage supply v c tracks the higher output supply v p . please see figure 2 below. t j 75 1.2 vtj ? 0.00384 ------------------------ + = figure 2. linear power tracking 1 2 15 14 13 12 6 7 8 11 10 9 20 19 el7564c - + 1 2 15 14 13 12 6 7 8 11 10 9 20 19 el7564c - + v c v p v out time v c v p
12 el7564c monolithic 4 amp dc:dc step-down regulator e l 7 5 6 4 c 2. offset tracking the intended start-up sequence is shown in figure 3a. in this configuration, v c will not start until v p reaches a preset value of: however, due to the superimpose of v c and v in , the choice of r a and r b are restricted by the following relationship: where 0.5 is for noise immunity. see figure 3 below. r b r a r b + -------------------- v in v p 0.5 r b r a r b + -------------------- v in r a r a r b + -------------------- + v c < + figure 3. offset power tracking v out time v c v p 1 2 15 14 13 12 6 7 8 11 10 9 20 19 el7564c - + 1 2 15 14 13 12 6 7 8 11 10 9 20 19 el7564c - + v c v p stp stn stp stn v in r a r b
13 el7564c monolithic 4 amp dc:dc step-down regulator e l 7 5 6 4 c the second way of offset tracking is to use the en and power good pins, as shown in figure 4. in this configu- ration, v p does not have to be larger than v c . figure 4. offset tracking v c 2 3 16 15 14 13 5 6 7 12 11 9 8 10 19 18 el7564c 2 3 16 15 14 13 5 6 7 12 11 9 8 10 19 18 el7564c 1 20 1 20 v p en pg en pg time v c v p
14 el7564c monolithic 4 amp dc:dc step-down regulator e l 7 5 6 4 c 3. external soft start an external soft start can be combined with auxilliary supply tracking to provide desired soft start other than internally preset soft start (figure 5). the appropriate start-up time is: t s rc v o v in --------- = figure 5. external soft start 1 2 15 14 13 12 6 7 8 11 10 9 20 19 el7564c - + v out stp stn v in r c
15 el7564c monolithic 4 amp dc:dc step-down regulator e l 7 5 6 4 c 4. start-up delay a capacitor can be added to the en pin to delay the con- verter start-up (figure 6) by utilizing the pull-up current. the delay time is approximately: t d ms () 1200 c m f () = figure 6. start-up delay 1 2 15 14 13 12 6 7 8 11 10 9 20 19 el7564c - + v out stp stn c time v o v in t d
16 el7564c monolithic 4 amp dc:dc step-down regulator e l 7 5 6 4 c thermal management the el7564cm utilizes ?fused lead? packaging tech- nology in conjunction with the system board layout to achieve a lower thermal resistance than typically found in standard so20 packages. by fusing (or connecting) multiple external leads to the die substrate within the package, a very conductive heat path is created to the outside of the package. this conductive heat path must then be connected to a heat sinking area on the pcb in order to dissipate heat out and away from the device. the conductive paths for the el7564cm package are the fused leads: # 6, 7, 11, 12, and 13. if a sufficient amount of pcb metal area is connected to the fused package leads, a junction-to-ambient resistance of 43c/w can be achieved (compared to 85c/w for a standard so20 package). the general relationship between pcb heat-sinking metal area and the thermal resistance for this package is shown in the performance curves section of this data sheet. it can be readily seen that the thermal resistance for this package approaches an asymptotic value of approximately 43c/w without any airflow, and 33c/w with 100 lfpm airflow. addi- tional information can be found in application note #8 (measuring the thermal resistance of power surface- mount packages). for a thermal shutdown die junction temperature of 135c, and power dissipation of 1.5w, the ambient temperature can be as high as 70c without airflow. with 100 lfpm airflow, the ambient tempera- ture can be extended to 85c. the el7564cre utilizes the 28-pin htssop package. the majority of heat is dissipated through the heat pad exposed at the bottom of the package. therefore, the heat pad needs to be soldered to the pcb. the thermal resistance for this package is better than that of so20. actual test results are available from elantec applica- tions staff. the actual junction temperature can be measured at vtj pin. since the thermal performance of the ic is heavily dependent on the board layout, the system designer should exercise care during the design phase to ensure that the ic will operate under the worst-case environ- mental conditions. layout considerations the layout is very important for the converter to func- tion properly. power ground ( ) and signal ground ( --- ) should be separated to ensure that the high pulse current in the power ground never interferes with the sensitive signals connected to signal ground. they should only be connected at one point (normally at the negative side of either the input or output capacitor.) the trace connected to the fb pin is the most sensitive trace. it needs to be as short as possible and in a ?quiet? place, preferably between pgnd or sgnd traces. in addition, the bypass capacitor connected to the vdd pin needs to be as close to the pin as possible. the heat of the chip is mainly dissipated through the pgnd pins. maximizing the copper area around these pins is preferable. in addition, a solid ground plane is always helpful for the emi performance. the demo board is a good example of layout based on these principles. please refer to the el7564c applica- tion brief for the layout.
17 el7564c monolithic 4 amp dc:dc step-down regulator e l 7 5 6 4 c package outline drawing (20-pin so package) note: the package drawing shown here may not be the latest version. for the latest revision, please refer to the elantec website at http://www.elantec.com/pages/package_outline.html
18 el7564c monolithic 4 amp dc:dc step-down regulator e l 7 5 6 4 c general disclaimer specifications contained in this data sheet are in effect as of the publication date shown. elantec, inc. reserves the right to make changes in the cir- cuitry or specifications contained herein at any time without notice. elantec, inc. assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. warning - life support policy elantec, inc. products are not authorized for and should not be used within life support systems without the specific written consent of elantec, inc. life support systems are equipment intended to sup- port or sustain life and whose failure to perform when properly used in accordance with instructions provided can be reasonably expected to result in significant personal injury or death. users con- templating application of elantec, inc. products in life support systems are requested to contact elantec, inc. factory headquarters to establish suitable terms & conditions for these applications. elan- tec, inc.?s warranty is limited to replacement of defective components and does not cover injury to persons or property or other consequential damages. o c t o b e r 3 , 2 0 0 1 printed in u.s.a. elantec semiconductor, inc. 675 trade zone blvd. milpitas, ca 95035 telephone: (408) 945-1323 (888) elantec fax: (408) 945-9305 european office: +44-118-977-6020 japan technical center: +81-45-682-5820

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